Generally, in the fabrication of an IC device, various processes may be utilized to etch/recess materials in cavities used in creating the circuits. The cavities may have different shapes or sizes and may be filled with different materials. For example, a cavity may include different layers of materials for spacers, gate dielectric, work-function metals, other dielectrics, or the like. Some of the current time-based etching processes include plasma etching of gap-fill materials followed by plasma or wet removal of the work-function metal. Another process includes pinching-off the gate cavity with work-function metal and plasma etching the work-function metal to reach a target recess depth. Such processes may require additional mask steps and processing time. Also, these etching processes may not be suitable for controlling the etching to a precise depth, where the recess depth may depend on a cavity dimension and be affected by plasma condition (e.g., etch chamfer stability).
FIG. 1 is a cross sectional diagram 101 of cavities in an example IC device, where a filling material 103 (e.g., gate metal) in cavities 105 is to be recessed to a recess depth level 107. However, as illustrated, the filling materials 103 in the cavities 105 are not recessed to a same level (e.g., level 107), as some are recessed to lower depths. For example, the filling materials 103 may include some imperfections such as seams 109 or voids/gaps 111 that may be present at different depths in the cavities 105, wherein the seams and/or voids may impact a target recess depth. Further, with work-function metal recesses formed by an ODL recess, the high-k dielectric may be chamfered for shorter gates to insure sufficient space for the ODL.
A need therefore exists for a methodology enabling recessing of materials in cavities, in an IC device, with precise depth control and the resulting device.